// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_profiling_s_cfg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/22 14:36:20 Create file
// ******************************************************************************

#ifndef __STARS_PROFILING_S_CFG_REG_OFFSET_FIELD_H__
#define __STARS_PROFILING_S_CFG_REG_OFFSET_FIELD_H__

#define STARS_PROFILING_S_CFG_SOC_ARSNOOP_PCIE_LEN         1
#define STARS_PROFILING_S_CFG_SOC_ARSNOOP_PCIE_OFFSET      12
#define STARS_PROFILING_S_CFG_SOC_ARCACHE_PCIE_LEN         4
#define STARS_PROFILING_S_CFG_SOC_ARCACHE_PCIE_OFFSET      8
#define STARS_PROFILING_S_CFG_SOC_ARSNOOP_SCHEDULER_LEN    1
#define STARS_PROFILING_S_CFG_SOC_ARSNOOP_SCHEDULER_OFFSET 4
#define STARS_PROFILING_S_CFG_SOC_ARCACHE_SCHEDULER_LEN    4
#define STARS_PROFILING_S_CFG_SOC_ARCACHE_SCHEDULER_OFFSET 0

#define STARS_PROFILING_S_CFG_SOC_AWSNOOP_PROF_LEN    1
#define STARS_PROFILING_S_CFG_SOC_AWSNOOP_PROF_OFFSET 12
#define STARS_PROFILING_S_CFG_SOC_AWCACHE_PROF_LEN    4
#define STARS_PROFILING_S_CFG_SOC_AWCACHE_PROF_OFFSET 8
#define STARS_PROFILING_S_CFG_SOC_AWSNOOP_LOG_LEN     1
#define STARS_PROFILING_S_CFG_SOC_AWSNOOP_LOG_OFFSET  4
#define STARS_PROFILING_S_CFG_SOC_AWCACHE_LOG_LEN     4
#define STARS_PROFILING_S_CFG_SOC_AWCACHE_LOG_OFFSET  0

#define STARS_PROFILING_S_CFG_SOC_AWNS_PROF_LEN         1
#define STARS_PROFILING_S_CFG_SOC_AWNS_PROF_OFFSET      17
#define STARS_PROFILING_S_CFG_SOC_AWNS_LOG_LEN          1
#define STARS_PROFILING_S_CFG_SOC_AWNS_LOG_OFFSET       16
#define STARS_PROFILING_S_CFG_SOC_ARNS_PCIE_LEN         1
#define STARS_PROFILING_S_CFG_SOC_ARNS_PCIE_OFFSET      1
#define STARS_PROFILING_S_CFG_SOC_ARNS_SCHEDULER_LEN    1
#define STARS_PROFILING_S_CFG_SOC_ARNS_SCHEDULER_OFFSET 0

#define STARS_PROFILING_S_CFG_SOC_ARPROT_PCIE_LEN         3
#define STARS_PROFILING_S_CFG_SOC_ARPROT_PCIE_OFFSET      3
#define STARS_PROFILING_S_CFG_SOC_ARPROT_SCHEDULER_LEN    3
#define STARS_PROFILING_S_CFG_SOC_ARPROT_SCHEDULER_OFFSET 0

#define STARS_PROFILING_S_CFG_SOC_AWPROT_PROF_LEN    3
#define STARS_PROFILING_S_CFG_SOC_AWPROT_PROF_OFFSET 3
#define STARS_PROFILING_S_CFG_SOC_AWPROT_LOG_LEN     3
#define STARS_PROFILING_S_CFG_SOC_AWPROT_LOG_OFFSET  0

#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_L_0_LEN    32
#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_L_0_OFFSET 0

#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_L_1_LEN    32
#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_L_1_OFFSET 0

#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_IS_VIRTUAL_0_LEN    1
#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_IS_VIRTUAL_0_OFFSET 17
#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_H_0_LEN             17
#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_H_0_OFFSET          0

#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_IS_VIRTUAL_1_LEN    1
#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_IS_VIRTUAL_1_OFFSET 17
#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_H_1_LEN             17
#define STARS_PROFILING_S_CFG_VPC_PMU_BASE_ADDR_H_1_OFFSET          0

#define STARS_PROFILING_S_CFG_JPEGE_PMU_BASE_ADDR_L_LEN    32
#define STARS_PROFILING_S_CFG_JPEGE_PMU_BASE_ADDR_L_OFFSET 0

#define STARS_PROFILING_S_CFG_JPEGE_PMU_BASE_ADDR_IS_VIRTUAL_LEN    1
#define STARS_PROFILING_S_CFG_JPEGE_PMU_BASE_ADDR_IS_VIRTUAL_OFFSET 17
#define STARS_PROFILING_S_CFG_JPEGE_PMU_BASE_ADDR_H_LEN             17
#define STARS_PROFILING_S_CFG_JPEGE_PMU_BASE_ADDR_H_OFFSET          0

#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_L_0_LEN    32
#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_L_0_OFFSET 0

#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_L_1_LEN    32
#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_L_1_OFFSET 0

#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_IS_VIRTUAL_0_LEN    1
#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_IS_VIRTUAL_0_OFFSET 17
#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_H_0_LEN             17
#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_H_0_OFFSET          0

#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_IS_VIRTUAL_1_LEN    1
#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_IS_VIRTUAL_1_OFFSET 17
#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_H_1_LEN             17
#define STARS_PROFILING_S_CFG_JPEGD_PMU_BASE_ADDR_H_1_OFFSET          0

#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_L_0_LEN    32
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_L_0_OFFSET 0

#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_L_1_LEN    32
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_L_1_OFFSET 0

#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_L_2_LEN    32
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_L_2_OFFSET 0

#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_L_3_LEN    32
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_L_3_OFFSET 0

#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_IS_VIRTUAL_0_LEN    1
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_IS_VIRTUAL_0_OFFSET 17
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_H_0_LEN             17
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_H_0_OFFSET          0

#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_IS_VIRTUAL_1_LEN    1
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_IS_VIRTUAL_1_OFFSET 17
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_H_1_LEN             17
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_H_1_OFFSET          0

#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_IS_VIRTUAL_2_LEN    1
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_IS_VIRTUAL_2_OFFSET 17
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_H_2_LEN             17
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_H_2_OFFSET          0

#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_IS_VIRTUAL_3_LEN    1
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_IS_VIRTUAL_3_OFFSET 17
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_H_3_LEN             17
#define STARS_PROFILING_S_CFG_VDEC_PMU_BASE_ADDR_H_3_OFFSET          0

#define STARS_PROFILING_S_CFG_PCIE_PMU_BASE_ADDR_L_LEN    32
#define STARS_PROFILING_S_CFG_PCIE_PMU_BASE_ADDR_L_OFFSET 0

#define STARS_PROFILING_S_CFG_PCIE_PMU_BASE_ADDR_IS_VIRTUAL_LEN    1
#define STARS_PROFILING_S_CFG_PCIE_PMU_BASE_ADDR_IS_VIRTUAL_OFFSET 17
#define STARS_PROFILING_S_CFG_PCIE_PMU_BASE_ADDR_H_LEN             17
#define STARS_PROFILING_S_CFG_PCIE_PMU_BASE_ADDR_H_OFFSET          0

#endif // __STARS_PROFILING_S_CFG_REG_OFFSET_FIELD_H__
